fm design radio

\r\nfollowing blocks need to be implemented IN VHDL with their test bench - read_iq, demod, decimating FIR, Deemph, qarctan \r\n\r\nthe module should be synthesizable and implemented with FIFO \r\n\r\nwith following conditions -\r\n\r\nC macros should be implemented as inlined VHDL functions\r\nUse the same quantization bit width as in the software.\r\nCreate a package with the array of filter coefficients and use generics to configure the filter taps and coefficients.\r\nHigh-level for-loops can be eliminated and replaced with streaming FIFOs\r\nUnroll internal function loops completely where applicable, such as shift registers\r\nApply one or more optimizations, such as loop unrolling or pipelining where applicable\r\nImplement the division algorithm discussed in class for the qarctan function.\r\nOptimize FIFO buffer sizes\r\n