Looking for Verilog Freelancer

Greetings, I'm a Digital IC designer, I have a very good knowledge of digital IC design in ASIC and FPGA using verilog, I've read your job and I know how to implement it in a good way. So, feel free to message me whenever you can so that I can know more about your needs. BR, Tarek

Hey there! I'm a professional electrical engineer having more than 4 years of experience. I'm an expert in verilog. I'll be waiting to hear back from you.

Hello dear, We are group of professional electrical electronics engineer verilog tutors expert and can do your task perfectly just text me so we can help you out with your task Kind regards

Hi I’m an Expert in verilog design and I’m interested in your project I can help you Send me a message to discuss the details

Verilog Expert Here I understand that you want to design adder Verilog based project, yes I will design it for you just in 4 to 5 hours from now. I am expert in this field and having 3 years working experience on Verilog based projects. Come on chat for more discussions Thanks

I have a lot of experienced in doing RTL Design with Verilog and Verification as well. I used to work as a Researcher at the OFDM Transciever group to make a lot of IP Core or module with Verilog such as Convolution Encoder, Puncture, Interleaver, Modulator, FIR Filter, Demodulator, Deinterleaver, Depuncture and Viterbi Decoder. Previously i was done a project with verilog and the client from Russia to make CRC with 1 bit error correction based on the algorithm that the client gave to me and i have done it <24/7. The other one is i used to solve or do debugging inside the verilog code why the waveform is not equal as expectation. Hopefully my skill and experienced could fulfill this project's requirements. Thank You

Dear Sir. ⭐⭐⭐Thank you for your job posting⭐⭐⭐ I am an Electronic engineer. I have 9 years experience in Verilog HDL& FPGA & Cadence & Modelsim. I checked your job carefully and I have a great interest in your project. I have many experience in your project. I'm sure of completing your project in the shortest time with high quality. If you hire me, then your project will be completed more successfully. I am waiting for good news. Best Regards Yana.

Hello Sir/Mam, I have done my mtech thesis on multiplier in which I have used different adders. I have experience in working with verilog , system verilog languages. I have worked on various protocols also. I can easily work on your project. Can we discuss more on it. Thanks Priyanka