I need VHDL Designer
₹1500-12500 INR
Paid on delivery
This is a final year project. We are struck with simulation. Need to debug our program, or else develop the project from scratch.
I am attaching the code that we have wrote for your reference.
We used Quartus altera for coding, and model sim for simulation. The development board is a cyclone 2.
There were no errors as such. The code would simulate and after one clock cycle, the output would become 'Z'.
From what I understood, the main issue is the interconnection between all the modules.
Project ID: #32325741
About the project
Awarded to:
I have 5 years practical experience in Digital System Design with VHDL and Verilog. I implemented different types IP cores and verified them. I also designed Simple Processors in my PhD period.