design with Altera FPGA

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I am an Electronics engineer who is very expertise with VHDL/Verilog. In fact, I have done so many project of VHDL/Verilog(Karatsuba multiplier, Nintendo design, encryption algorithm like Sax Hash, Bernstein Hash, HummingBird...Also, I participated in a Walker Recognition project(data from Camera to Human Detection(image processing-HOG feature and Adaboost) and display in VGA). Besides,,I implemented the image conpression (wavelet transform). Aslo, I have experience in coding Booth multiplier and very familiar with Xilinx tools like ISE. and Vivado. Therefore, I can simulation the projecthe in behavior, post-syntheize... with free hesitation. I am also have experience of freelancer here: https://www.freelancer.com/u/ducdctoandh.html Also, I am very good in English (IELTS 6.0) and I have several year of researching so I can fully understand your requirement and understand fully about the papers and write the academic report. Please contact me and let me know if you want any special requirement and do with lower price. Thank you.

I am Electronics Engineer. My Expertise are MATLAB, Simulink, AUTO CAD, Pro E, Verilog, Python, PSSE, PWS, PSS Sincal, ORCAD, Altium(PCB design pursuit) ,MPLAB, Xilinx (VHDL, HDL). PLC, SCADA Systems, Wireshark and packet tracer. I can show you my work samples. My work completion rate is 100% and 25% repeat hire rate. I provide 100% satisfactory work to my clients therefore, i have best feedbacks and reviews from my respected clients. Thank you for considering the proposal. Regards Asad

Hi there, I have experienced in VHDL design and Timing closure analysis. I also familiar with Xilinx and Intel tools design. please take a look via my profile. thanks.

I can compile with Precision RTL and/or Synplify. Do you have the constraints defined in plain text ?