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$10 USD / hour
Flag of INDIA
karur, india
$10 USD / hour
It's currently 6:40 PM here
Joined March 17, 2021
0 Recommendations

Senthil P.

@senthilps3

5.0 (19 reviews)
4.2
4.2
95%
95%
$10 USD / hour
Flag of INDIA
karur, india
$10 USD / hour
100%
Jobs Completed
89%
On Budget
84%
On Time
14%
Repeat Hire Rate

VLSI/FPGA/ASIC/PCB design/RF Antenna

I am a researcher in hardware security and a circuit designer for floating-point arithmetic cores, DSP cores in HDL/schematic. I have the scientific journal published in these areas with patent. I assure you that your needs will be fulfilled in an HDL/circuit schematic with optimized for area, delay, and speed point of views. Additionally, pipeline, datapath subsystem, and static timing analysis in digital circuit implementation are performed. Specialist in hardware architectures for arithmetic blocks, signal processing, cryptography, machine learning architectures and computer architecture Having 10 years experience in hardware design, verilog/VHDL and circuit simulation at Intel Quartus II, Cadence SoC encounter/RTL compiler, LTspice, Logisim and Microwind DSCH DOMAINS VLSI- ASIC/FPGA CMOS layout CMOS stick diagrams Physical design Digital hardware implementation AI hardware in VLSI Microprocessors and Micro controller implementations in FPGA DSP/Embedded Hardware High-level algorithms into hardware Computer Architecture Network on chip Memory circuit design Finite state machine design SKILLS Verilog/VHDL TCL script A circuit schematic, state machine/table, RTL coding Pipeline, retiming, Cross-domain clocking, High level synthesize Asynchronous timing, bus protocols (AMBA, PCIe, SPI, I2C) TOOL EXPERT Quartus II prime EDA Cadence NCSIM- verilog simulation Cadence RTL compiler Cadence SoC encounter/180 nm technology node Modelsim Microwind Logisim LTspice Ledit Xilinx VIvado HLS

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Portfolio

9642327
9572153
9573048
9572143
9572131
9572124
9642327
9572153
9573048
9572143
9572131
9572124

Reviews

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Showing 1 - 5 out of 19 reviews
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5.0
$30.00 CAD
The project was done on time and was delivered as requested, perfectly done. easy to contact and well understanding on the project and the requirements
D
Flag of Dharkashan S.
@dharkashan5
•
4 months ago
5.0
$450.00 USD
Professional. Timely delivery. Would work again with him
Engineering
Electronics
Technical Writing
Electrical Engineering
Word
+8 more
User Avatar
Flag of Aditya L.
@aditya2212
•
6 months ago
5.0
$50.00 USD
Senthil is an expert and extremely knowledgeable in VHDL. He was able to deliver the project on time and in budget. Looking to work with them again.
Electronics
Verilog / VHDL
Microcontroller
FPGA
Very-large-scale integration (VLSI)
I
Closed User
@iotpvtltd
•
1 year ago
5.0
$20.00 USD
he is the awesom and best freelancer which had ever work ever work for me
C Programming
Verilog / VHDL
Microcontroller
Electrical Engineering
Microsoft Visio
User Avatar
Flag of Yash S.
@kunwaryash51
•
2 years ago
5.0
$45.00 USD
Great to work with. And delivers on time
B
Flag of Thejaswini Reddy B.
@Bhee1
•
2 years ago

Experience

Assistant professor/research scholar

Chettinad College of Engg and tech
Dec 2011 - Dec 2018 (7 years)
I have experience in the position of teaching faculty in ECE and 2014 onwards I started my research carrier in Floating point arithmetic, hardware security and VLSI datapath subsystem design

Education

Ph.D VLSI design

Anna University, India 2014 - 2021
(7 years)

Publications

Design a Hybrid FPGA Architecture for Visible Digital Image Watermarking in Spatial and Frequncy dom

Journal of Circuits, Systems and Computers/ World Scientific publisher, Singapore
Hybrid field programmable gate array (FPGA) implementation is proposed to improve the performance of visible image watermarking systems. The visible watermarking process is implemented as pixel by pixel operation under a spatial domain or vector operation in the frequency domain. The proposed approach is mainly designed for watermarking the images taken from digital cameras of various sizes. The padding technique is used for unequal sizes of the watermark image and original host image.

Alleviation of Data Timing Channels in Normalized/Subnormal Floating Point Multiplier

Journal of Circuits, Systems and Computers/ World Scientific publisher, Singapore
Execution time variations create unintentional delay and data timing channels (DTCs). A circuit is proposed for floating-point multiplication to minimize the unintentional delay for the holistic support of subnormal numbers. In this proposed four-path FP multiplication, the circuit produces the four types of output in four paths having different delays for all cases of input combination. These four paths are establishing the DTCs.

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