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UVM verification of memory controller - open to bidding

$30-250 USD

Closed
Posted over 6 years ago

$30-250 USD

Paid on delivery
Need someone to verify a memory controller using UVM environment. CAN bus is used as a memory cycle initiator and write/read burst transactions need to be verified.
Project ID: 15695560

About the project

4 proposals
Remote project
Active 6 yrs ago

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4 freelancers are bidding on average $430 USD for this job
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Hello! Please check my reviews and profile to know more about me and my work. Thank you! Relevant skills and experience Verilog 4+ years UVM 2+ years
$222 USD in 7 days
5.0 (81 reviews)
6.0
6.0
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I am doing this work on daily basis in my company projects and this can be done easily by me and with 100 % efficiency. Relevant Skills and Experience UVM, System Verilog, CAN Proposed Milestones $200 USD - After 50% work $77 USD - after 100 % work Would you providing system to do this work or I'll have to use my work system?
$277 USD in 2 days
0.0 (0 reviews)
0.0
0.0
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I'd been working as UVM verification engineer for more than 15 years. The project that I'd been working ranging from block level such as MAC, PCIe PHY, MIPI to million gate count of SOC. Relevant Skills and Experience I'd been verify IP ranging from block level such as MIPI, DDR, PCIe PHY, and many more as well as many SOC level verification for more than 15 years. Proposed Milestones $666 USD - building the test bench as well as compete automation suite Can you provide me the requirement of this project ? And how in depth of verification you need ?
$666 USD in 5 days
0.0 (0 reviews)
0.0
0.0

About the client

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United States
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Member since Nov 20, 2017

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