I am a senior year PhD Scholar at Shanghai Jiao Tong University, Shangahi China. My research is all about Reconfigurable Computing /Fast Arithmetic Circuits / Efficient Neural Network Accelerator Design, as you know its all connected with Verilog HDL. I have been working with Verilog HDL fro more tahn 5 years. I am pretty comfortable not only with writing Verilog HDL Code for simple to very complex systems such as DSP systems/ Embedded Control Systems and currently i am, developing Neural Network Accelerator Design which will be available on my github very soon.
I have also written Custom IP Core packaging in to industry standard interfaces such as Xilinx AXI- Stream, AXI-Lite and AXI4 interfaces. In conclusion, i can code your design in Verilog RTL providing functional simulation as well as synthesis on a device (FPGA, SoC or mixed FPGA-SOC solution.