I am a graduated electronics engineer from faculty of engineering Cairo university with very good with honor grade,4 years experience in Verilog, I have done a lot of projects using Verilog &VHDL also my graduation project was the implementation of 5G receiver using Verilog
My Verilog projects: state machines, clock divider, clock gating, ALU , 16-bit mips , UART ,SPI , CRC , interleaver , Demapper, Register file ...