Modeling timing uncetanity in communication

We are a team of Electrical and Electronics engineers, we have successfully completed 1000+ Projects for multiple regular clients from OMAN, UK, USA, Australia, Canada, France, Germany, Lebanon and many other countries More

Hello, I am contacting you to work on your project. I completed a similar project before. Please contact me to discuss more details.

I have a lot of experienced in doinf RTL Design with Verilog and Verification as well. I used to work as a Researcher at the OFDM Transciever group to make a lot of IP Core or module from Verilog such as Channel Coding More