conversion using specific logic on verilog files

Hi, I am competitive to this kind of task, can take good care of this project. In fact, I already done related to this job before. Let me know the best of your time so we can discuss further based on your requirements and we can move forward to the next step. Thanks, Joseph C Ocero

Hi. This will be a needed amount to done this task. kindly let me know about the task. Waiting for your reply