VHDL task using Xinlinx Vivado

Completed Posted 5 years ago Paid on delivery
Completed Paid on delivery

A task compromising of Counter, clock divider, clock enable (CE), and seven-segment display using VHDL and Xinlinx Vivado.

Further details will be provided.

Deadline 3 days.

Electrical Engineering Electronics Engineering FPGA Verilog / VHDL

Project ID: #18077616

About the project

2 proposals Remote project Active 5 years ago

Awarded to:

ahmedmohamed85

Dear sir I have more than 10 years experience in digital design using Xilinx FPGA and vivado please check my profile also please message me so that we can discuss

$30 USD in 1 day
(378 Reviews)
7.8