simple fpga addition subtraction code -- .

I have a lot of experience in the digital design field. I can - Write the source code for your design - Wite a self-checking testbench to test the functionality of the design - Write a mapping file to map the design to the FPGA kit - Automate the simulation process using .do scripts I am looking forward to working with you. Thanks

hello, ı m electrical engineer and ı have finished many projects I know FPGA normal level and I can do let me discuss

Hi, FPGA and Embedded system expert here. I already have my own code (IP core) written for adder-subtractor in verilog and VHDL. I'm willing to sell it. Please contact me and we can discuss further details. thanks

Hands on experience working with Xilinx ISE and Vivado

Dear Sir/Madam, I have been working as freelancer for last 2 years. Here is summery of my experience : * FPGA firmware development of multi-channel data acquisition system. * Verilog implementation of windowed image computation and Kalman filter for object tracking. * Verilog implementation of RBM( deep learning) algorithm. * RTL integration of AES encryption/decryption RTL module with SHA 256 RTL module from github and using it as AXI peripheral for AXI interface of zedboard. As a full time employee , I have experience in ASIC verification of design in System verilog, VIP development and module level RTL coding. I would like to work on your project and finish it with utmost satisfaction of yours. If my profile is suitable for your job requirement, please ping me. Thank you.

Hi, glad to bid on your project. I have read your description, i have a 15+ years of experience on development and research papers solutions on following Matlab & Simulink , Python and good at VHDL Verilog Spice, R software programming Numerical analysis with Mathematica, CFD Applications and Matlab for mechanical applications

I can do this I have specialization in following: Embedded System Design based on • Digital System Design (FPGA, CPLD) • Signal and Image Processing Algorithms • Micro-Controllers & Processors  Hands on experience on following platforms: 1) Xilinx heterogeneous architectures: ZYNQ 7020, 7035 and 7045 SOC FPGAs. 2) ZYNQ 702 and 706 FPGA boards. 3) Xilinx low power FPGAs Artix 7, Nexys 2,3 and 4 boards. 4) Xilinx low density Spartan FPGAs. Spartan 3E FPGA development kit. 5) Trenz TE0782 & TE0783 SOM FPGA boards. 6) Intel: Cyclone 10 FPGA development kit. 7) Analog devices: Realtime 3G/4G SDR based ADI RF integrated devices. 8) Atmel AVR microcontroller ATmega16/32/328, Arduino (Uno, Mega & Nano), (PIC based) chip kit.

Ill send the project in 30 mins..............................................................................................

I am sr. RTL design engineer. I can do your work very easily and perfectly. I will provide you synthesizable code, testbench along with reports followed by detail description.

good in verilog ... Relevant Skills and Experience have done many project with verilog related

Hello, I can do it using vhdl. I have already made a project using vhdl that uses alot of mathematical operations. If you need complex mathematical operations i can do it also using xilinix ip cores with minimum utilization. Time and salary depends on the project intended.

I am a Nanoelectronics Engineer. I am mainly interested in digital electronics and machine learning. I have worked on the hardware design and implementation of Convolutional neural networks and spiking neurons. I have had experience with vivado tool, as well as, many FPGA platforms; such as, Xilinix Zynq and Virtex UltraScale+. I have already designed and implemented an ALU composed of a full adder/subtractor, shifter and multiplier. I would be happy to help u with your project.

I going to write a VHDL and testbench for your adder substracter

+923048412568 this is my whatsapp number, im doing computer engineering, and yes i know verilog, last smester was all about this, i can help..

Nothing is simple when you work with the FPGAs. When you design adder/subtractor on FPGA, you have to look the signed number first. Then you might have overflow/underflow cases. I can help you with this as I am teaching this from last 8 years.