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Floating-point Unit Development(Quartus Prime Verilog)

$30-250 AUD

Completed
Posted almost 5 years ago

$30-250 AUD

Paid on delivery
In this project, you are required to develop a structural Floating-Point Unit (FPU) for use with a microprocessor. The processor needs to be capable of floating point addition and multiplication. The numbers are to be encoded into IEEE 754 single precision 32-bit format. The FPU should also be able to detect and flag the 'NaN' cases. For the project demonstration, interface the FPU to the DE-10 RAM and perform the operation A*B+C on 1000 data triplets (A, B, C). Transfer the results back to the RAM, then upload to the PC for display. Verify the results by comparing them with another method (e.g., C program, spreadsheet etc.). This project Must be built using Quartus Prime's Verilog code. A code example is attached, you can follow the example but please modify it to fit my project description.
Project ID: 19729832

About the project

2 proposals
Remote project
Active 5 yrs ago

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Dear sir I have more than 10 years experience in digital design using Quartus, please message me so that we can discuss
$364 AUD in 2 days
4.9 (511 reviews)
8.2
8.2
2 freelancers are bidding on average $232 AUD for this job
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I have 10 years of experience in design and verification using Verilog. Please message me. Best regards.
$100 AUD in 3 days
5.0 (8 reviews)
4.2
4.2

About the client

Flag of AUSTRALIA
melbourne, Australia
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