I am looking for someone whi knows Vivado 16.4 Webpack to write and simulate some simple VHDL files. These are basic tasks and i can share more details like required input and output.
My name is Roman, I wokr as FPGA designer and we use Xilinx tools. I familiar with work in XILINX Vivado tools as well. I glad to help you with your task. Just let me know details.
Hi, I have 14 years of research and industrial experience and I am proficient in vhdl. I have very good knowledge in vivado. Please let me know whats your requirement.