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    2,000 vhdl project vhdl project jobs found, pricing in USD
    Make changes to a verilog code Ended

    Hi, I am looking for someone with experience in verilog/VHDL programming or with Electronics background to modify some code. Details and files will be given in chat in what needs to be done in the code.

    Electronics Embedded Software Verilog / VHDL
    $23 (Avg Bid)
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    19 bids
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    i need help in vhdl task Ended

    already i have algorithm i must implement it and i have suggested solution can be implemented easily by any expert vhdl programmer , i'm a student i have a very simple background in vhdl programming ... my budget is very simple becouse i'm student around 50$ per project .. thanks in advance for your time

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    $10 (Avg Bid)
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    1 bids
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    VHDL code using xilinx synthesis Ended

    i have already algorithm and suggestion to implement vhdl code to apply it

    Algorithm FPGA Verilog / VHDL
    $29 (Avg Bid)
    $29 Avg Bid
    9 bids
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    FPGA NEXYS4 DDR using ISE program (Xilink) VHDL Ended

    Using ISE VHDl , I need someone to continue to do my lab as i I have in the attachment files lena pic and the inversion of pixels in lena image, I want someone to do one program for 2D filters regarding smoothing lena pic and another program to do the sobel of lena pic. easy work will not take long time.

    Electronics FPGA Microcontroller Verilog / VHDL
    $324 (Avg Bid)
    $324 Avg Bid
    6 bids
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    Very Urgent VHDL task with report Ended

    Hi I have a VHDL task and need to be done on very urgent basis. I can give you detail once you bid. Please bid only if you can deliver it within 24 hours. I am waiting for your reply Regards

    Electrical Engineering Electronics FPGA Verilog / VHDL
    $128 (Avg Bid)
    $128 Avg Bid
    23 bids
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    Ring Oscillator (RO) Physical Unclonable Functions (PUFs) Ended

    about Ring Oscillator (RO) Physical Unclonable Functions (PUFs). Additionally, a sub-objective is to gain further experience with the Xilinx ISE simulation environment and VHDL.

    Verilog / VHDL
    $180 (Avg Bid)
    $180 Avg Bid
    4 bids
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    VHDL(FPGA) Ended

    i need very fast implementation for custom formula ..... pales note maximum budget is 50$/per project

    Algorithm FPGA Verilog / VHDL
    $29 (Avg Bid)
    $29 Avg Bid
    8 bids
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    H.265/HEVC codec Ended

    Need to develop H.265/HEVC CABAC decoder Verilog/VHDL code

    FPGA Software Architecture Verilog / VHDL
    $1244 (Avg Bid)
    $1244 Avg Bid
    8 bids
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    image processing fpga implementation Ended

    i have an fpga algorithm fully compatible for conversion to verilog. vhdl. i need some expert to define the acticture re assemble it and test it on fpga. i have some verilog implementation code for it too.

    Electrical Engineering Medical Writing PDF Report Writing Technical Writing
    $190 (Avg Bid)
    $190 Avg Bid
    7 bids
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    VHDL Implementation of Reduced Complexity Wallace Multiplier using Energy Efficient CMOS Full Adder and Performance Analysis Ended

    Implementation and Performance Analysis of RCWM using EECFA

    Verilog / VHDL
    $211 (Avg Bid)
    $211 Avg Bid
    2 bids
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    VHDL task need to done with Report Ended

    Hi I need a small report with VHDL programming Budget is 50 USD max anyone who is interested should bid timeline is 5 days Only serious persons should bid Thanks

    C Programming Electrical Engineering Electronics Engineering Verilog / VHDL
    $42 (Avg Bid)
    $42 Avg Bid
    15 bids
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    Design Digital clock using VHDL Ended

    Hello I want a vhdl code for a digital clock to present hours, minutes and seconds in board Altera DE2 -115 Cyclone IV. The code should be written by the freelancer him/her self not from copy from internet. A report should be included . With line by line explanation of code Thank you

    Electrical Engineering Engineering Verilog / VHDL
    $118 (Avg Bid)
    $118 Avg Bid
    20 bids
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    Multiplication Unit in the AMBER ARM Core (VHDL) Ended

    Use Xilinx ISE design suite to implement and validate the multiplication unit in the AMBER ARM core. As we have studied in class, the unit uses radix-2 Booth’s recoding to perform the multiplication. It can also perform multiply-and-accumulate operation. You need to fully understand all the details of the multiplication ISA and the multiplication Verilog module implementing it including all different modes of operation and control. You are also required to validate the design on the Nexys3 board. Also, use Tektronix logic analyzers or digital oscilloscopes in our labs to be able to see the signals.

    Software Architecture Verilog / VHDL
    $90 (Avg Bid)
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    5 bids
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    a game using the Altera DE2 Board Ended

    A game using the LEDs on the DE2 Board. These lights will chase. The object of the game is for the user to "catch" the LED light by moving the switch up at the moment the LED light is on above the switch. The light is to restart once the switch is moved back down. Score should be recorded in the HEX display. VHDL code, flip flops, clocks, and other logic devices are fare game. Everything has to be done in Quartus though.

    Verilog / VHDL
    $184 (Avg Bid)
    $184 Avg Bid
    12 bids
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    The project is to design an energy saving traffic light controller on FPGA. Ended

    The use of energy saving traffic light controller presents a significant opportunity for local government to lower energy bills and improve the quantity of lighting service [1]. Thus, the project is to design an energy saving traffic light controller on FPGA. The traffic light controller(TLC) includes a simple traffic light on FPGA with VHDL language and an embedded project which uses TSK3000 to design a timer to turn on or turn off the traffic light depending the day and night and process the data from the vehicle sensor in real time. The result will display on the Nanoboard 3000. TSK3000 is 32-bit FPGA-based RISC processor [2].

    Digital Design Electrical Engineering Electronics Energy Engineering
    $326 (Avg Bid)
    $326 Avg Bid
    7 bids
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    Lattice ECP3 VHDL/Verilog Programmer Ended

    Project based on PCIe core. The logic is implemented on top of the PCIe core and the memory map is used to access the registers. The code and concept is ready. We need someone who can efficiently code and do the PAR. Entire development is on ECP3 Versa Development board. Project duration is 2/3 weeks.

    FPGA Verilog / VHDL
    $746 (Avg Bid)
    $746 Avg Bid
    6 bids
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    Easy VHDL Project Ended

    I have few VHDL questions. Only expert is needed for this.

    Verilog / VHDL
    $21 (Avg Bid)
    $21 Avg Bid
    11 bids
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    VHDL coding Ended

    VHDL coding for CPLD device to test signals of TTL,differential,SPI etc.

    Verilog / VHDL
    $131 (Avg Bid)
    $131 Avg Bid
    11 bids
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    FPGA VHDL code Ended

    i need professional vhdl programmer to design described algorithm

    FPGA Verilog / VHDL
    $27 (Avg Bid)
    $27 Avg Bid
    14 bids
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    Advanced Design System (ADS) - Agilent / Keysight -- RF PCB design Ended

    RF signal generator PCB - RF spectrum analyzer PCB. The project require Advanced Design System (ADS) - Agilent / Keysight RF PCB design or equivalent RF simulation. The PCB require specifically RF design skills. More details on PM. C, C++, MATLAB, VHDL, VDSP, ModelSim are a plus.

    Circuit Design Electrical Engineering Matlab and Mathematica PCB Layout Telecommunications Engineering
    $1500 - $3000
    Featured Sealed NDA
    $1500 - $3000
    11 bids
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    Logic Design VHDL Simulation Ended

    The job involves simulation in VHDL. Looking for a long-term collaboration.

    Electrical Engineering Engineering
    $14 (Avg Bid)
    $14 Avg Bid
    9 bids
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    Write some Software Ended

    FPGA using VHDL langauge.

    PHP Software Architecture
    $100 (Avg Bid)
    $100 Avg Bid
    5 bids
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    R-type and I type Implementation on Basys-II Board -- 2 Ended

    I'm interested in finding a freelancer that will help me with 4 different projects( Each project will be a different job) that I will make available as you help me. These projects are twofold: you deliver the project and explain to me everything you have done in a detail manner. In addition, you explain to me the reasoning behind your logic. The first project will be designing a R_type_datapath using vhdl and implementing different components in basys II board. More details will be provided if you ask for them. This is a private job

    FPGA Verilog / VHDL
    $230 (Avg Bid)
    $230 Avg Bid
    8 bids
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    Verylog or VHDL 4 bit accumulator with reset Ended

    Hi Looking for person familiar with Verylog VHDL 5-7 hours of work. Deadline is 3 days. Will post details for bidders.

    Electronics Verilog / VHDL
    $22 (Avg Bid)
    $22 Avg Bid
    5 bids
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    Verylog or VHDL 4 bit accumulator with reset Ended

    Hi Looking for person familiar with Verylog VHDL 5-7 hours of work. Deadline is 3 days. Will post details for bidders.

    Electronics Verilog / VHDL
    $30 (Avg Bid)
    $30 Avg Bid
    14 bids
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    Design project Ended

    I need a professional who has skill in VHDL using Quartus 15 64bit Altera DE2 board to do a job for me

    Branding Corporate Identity Graphic Design Logo Design Website Design
    $345 (Avg Bid)
    $345 Avg Bid
    9 bids
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    cncerning vhdl Ended

    The objective is to design a 5-bit. you can do it. it is very easy to do . complete design and testbench code

    Electrical Engineering Engineering Mathematics Matlab and Mathematica Verilog / VHDL
    $20 (Avg Bid)
    $20 Avg Bid
    1 bids
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    Design me a Product Ended

    automotive embedded systems verilog vhdl c programming

    Automotive C Programming Embedded Software Product Design
    $599 (Avg Bid)
    $599 Avg Bid
    14 bids
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    Build a Website Ended

    automotive embedded projects infotainment systems open gl vhdl verilog programming for architectures

    Automotive C Programming Embedded Software HTML Verilog / VHDL
    $714 (Avg Bid)
    $714 Avg Bid
    12 bids
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    Network Engineering homework Ended

    Have a look at the problem set and let me know if you can do it. VHDL and verilog equivalent. and 5 questions work for network that needs to get done. bid on it if you have the skill set and i will assign. When you open this file you will find the 2 works that need to be done

    Cisco Electrical Engineering Network Administration Python
    $248 (Avg Bid)
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    7 bids
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    VHDL coding Ended

    VHDL project stop watch coding

    Verilog / VHDL
    $165 (Avg Bid)
    $165 Avg Bid
    1 bids
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    VHDL project Ended

    design a code in vhdl language, make a stop watch

    Verilog / VHDL
    $93 (Avg Bid)
    $93 Avg Bid
    21 bids
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    Lattice ispLSI1032 CPLD Project For Review Ended

    ...help resolve issues I’m experiencing. I have a project that is experiencing what I believe to be timing issues. The project is an 8Meg RAM Card for an Apple IIgs, and there are 2 versions of this computer (ROM1 and ROM3). Both have slightly different timings, but are basically compatible. I currently have a proto PCB I am working with. The project is laid out using Schematic Entry since I have no VHDL knowledge. I have been adding gates and setting net attributes in order to adjust timings in an attempt to achieve a design that works on both versions of the Apple IIgs. I believe if the address and /CAS and /RAS signals could all be latched or clocked, then the design would be stable, however I'm open at all ideas. The project ...

    Circuit Design Electrical Engineering Electronics FPGA
    $30 - $250
    $30 - $250
    0 bids
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    SCAN PATH TEST FOR STUCK AT FAULTS Ended

    In this lab, you will design and implement a state machine in VHDL. You will include additional circuitry in the design so that you can use scan path testing to verify your state machine. You will simulate the scan path testing in Xilinx ISE and synthesize your design so that you can see the extra resources required for the scan logic. An additional sub-objective is to get more familiar with the Xilinx ISE environment.

    Verilog / VHDL
    $35 (Avg Bid)
    $35 Avg Bid
    1 bids
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    design of wallace multiplier using energy efficient adder Ended

    Required VHDL design and implementation of Wallace multiplier using a new kind of adder.

    Verilog / VHDL
    $225 (Avg Bid)
    $225 Avg Bid
    14 bids
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    Need to do VHDL task using altera Ended

    please check the attached task i want this to be done in 3 hrs

    Electronics Matlab and Mathematica PCB Layout Telecommunications Engineering Verilog / VHDL
    $67 (Avg Bid)
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    5 bids
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    need urgent VHDL task related to modelsim Ended

    pls check the attachment.. i want this to be done fast

    Verilog / VHDL
    $22 (Avg Bid)
    $22 Avg Bid
    4 bids
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    URgent VHDL task to finish now Ended

    Please check the attachment.. i want to complete this in 2 or 3 hrs

    Electrical Engineering Electronics Matlab and Mathematica Microcontroller Verilog / VHDL
    $20 (Avg Bid)
    $20 Avg Bid
    3 bids
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    Rectify programming error in VHDL Ended

    Simple project. only need to rectify error so the program can compile. Do note that this program i'm doing is on partial reconfiguration.

    Electrical Engineering FPGA Verilog / VHDL
    $18 (Avg Bid)
    $18 Avg Bid
    11 bids
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    R-type Instructions Implementation on Basys-II Board Ended

    I'm interested in finding a freelancer that will help me with 4 different projects( Each project will be a different job) that I will make available as you help me. These projects are twofold: you deliver the project and explain to me everything you have done in a detail manner. In addition, you explain to me the reasoning behind your logic. The first project will be designing a R_type_datapath using vhdl and implementing different components in basys II board. More details will be provided if you ask for them. This is a private job

    FPGA Verilog / VHDL
    $186 (Avg Bid)
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    3 bids
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    Project for ahmedmohamed85 Ended

    Hi ahmedmohamed85 I noticed on your profile and would like to offer you my project. We can discuss any details in the chat. My project is ov7670 camera interfacing with spartan 3 and vhdl.

    Electrical Engineering Electronics Engineering Microcontroller Verilog / VHDL
    $35 / hr (Avg Bid)
    $35 / hr Avg Bid
    1 bids
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    need to do vhdl modelsim Ended

    need to do this task asap using modlsim

    Verilog / VHDL
    $21 (Avg Bid)
    $21 Avg Bid
    12 bids
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    assignment Ended

    just as home work. you are asked to design the phase locked loop (PLL) system using digital system design . Get the VHDL code for this PLL system

    Electronics Verilog / VHDL
    $27 (Avg Bid)
    $27 Avg Bid
    15 bids
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    Vlsi Project Ended

    I need two projects on VLSI design using verilog/vhdl language with complete coding and documentation.

    Verilog / VHDL
    $103 (Avg Bid)
    $103 Avg Bid
    23 bids
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    Project: Verilog, FPGA, VHDL, Embedded C Ended

    A project needs to be developed to be done on FPGA, further details to be shared on PM.

    Assembly C++ Programming FPGA Matlab and Mathematica Verilog / VHDL
    $144 (Avg Bid)
    $144 Avg Bid
    1 bids
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    I need your help in writing c code for a circuit Ended

    I need your help in writing c code for chasing led circuit (VHDL) please check attached file for details can pay 10 $ and best review and need in an hour or 2

    C Programming Verilog / VHDL
    $19 (Avg Bid)
    $19 Avg Bid
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    video showing how to run the code and showing resluts on fpga... Ended

    i have the vhdl code for a project... i need it to be run and make a video explaining clearly the steps to run it on fpga..

    FPGA Verilog / VHDL
    $16 (Avg Bid)
    $16 Avg Bid
    10 bids
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    Design and implementation of MPEG-2 encoder on Altera FPGA Ended

    Design an MPEG-2 encoder IP Core in Verilog or VHDL to compress a video signal resolution 640x480. The input images will be in the YCrCb color space. The IP core arquitecture should be Pipeline.

    C Programming FPGA Verilog / VHDL
    $1441 (Avg Bid)
    $1441 Avg Bid
    13 bids
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    Implementation of multi resolution filter bank in fpga Ended

    I want to implement two types of multi resolution filter banks : using coefficient decimation method, and using frequency response masking method ,the implementation should be done using fpga kit (altera),using vhdl code.

    Matlab and Mathematica Verilog / VHDL
    $221 (Avg Bid)
    $221 Avg Bid
    8 bids
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    Write a para Ended

    Write a para each on each of the following. 1. Image Processing and FPGAs 2. VHDL 3. Image Capture 4. Image Filters Convolution and Morphology 5. FPGA Based Design and Algorithm Implementation 6. Histogram Processing

    Research Writing
    $15 (Avg Bid)
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