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    2,000 vhdl project vhdl project jobs found, pricing in USD
    electronic and VHDL Ended

    Design a colour processor to extract U and V signals, and collect colour data. Test it in SignalTap Use it to capture a training colour Test with golf ball presented in the field of view Train on ball colour. Ball will be placed about 10cm directly in front of robot. Make robot dribble the ball. i have coded evey elements i just need some changed

    Engineering Software Architecture Software Testing
    $187 (Avg Bid)
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    digital control Ended

    Combination Lock State Machine Design Using VHDL

    C Programming
    $167 (Avg Bid)
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    Combination lock state machine design using VHDL Ended

    I need to do some vhdl coding for a lock. i will give more information to the bidders

    Electronics Verilog / VHDL
    $101 (Avg Bid)
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    VHDL code for IR sensor to measure the distance and display on lcd - open to bidding Ended

    I need VHDL codes with tester and testbench and also excute correctly. i need the circuit diagram for this if possible.

    Algorithm Electronic Forms Electronics Embedded Software Verilog / VHDL
    $171 (Avg Bid)
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    4 Digit Security system(vhdl code) Ended

    I want the vhdl code for the 4 digit security system and the compilation screen shot

    Article Writing Content Writing Copywriting Ghostwriting
    $15 (Avg Bid)
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    VHDL code for IR sensor to measure the distance and display on lcd Ended

    I need VHDL codes with tester and testbench and also excute correctly. i need the circuit diagram for this if possible.

    Algorithm Electronic Forms Electronics Embedded Software Verilog / VHDL
    $100 (Avg Bid)
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    128 bit to 32 bit Conversion Ended

    I would like to convert my 128 bit input and 128 bit output to become 32 bit for both input and output without changing the algorithm using VHDL. This project is about the key schedule of AES Rijndael. You can get the overview of the project through this website (page 17 onwards) If you are agree to accept this project I will send you my original codes.

    Verilog / VHDL
    $43 (Avg Bid)
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    7 bids
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    Writing Code with VHDL on FPGA Ended

    writing some code on vhdl to complete the mission.

    Electrical Engineering FPGA Matlab and Mathematica Verilog / VHDL
    $195 (Avg Bid)
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    15 bids
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    Write some Software - VHDL -FPGA Ended

    writing some code related with FPGA and VHDL

    FPGA Verilog / VHDL
    $28 (Avg Bid)
    $28 Avg Bid
    5 bids
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    Building a VGA Display Driver, I/O Driver, and Memory Mapping Ended

    Specifics in attached .pdf's Supporting source code will be supplied. For someone with SystemVerilog/VHDL/FPGA/ASM experience this shouldn't take more than a few hours. Must be completed by 4/26/2016 - Willing to negotiate Bonus if completed sooner.

    Assembly Digital Design FPGA Verilog / VHDL x86/x64 Assembler
    $189 (Avg Bid)
    $189 Avg Bid
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    Building a VGA Display Driver, I/O Driver, and Memory Mapping! Ended

    Specifics in attached .pdf's Supporting source code will be supplied. For someone with SystemVerilog/VHDL/FPGA/ASM experience this shouldn't take more than a few hours. Must be completed by 4/26/2016 - Willing to negotiate Bonus if completed sooner.

    FPGA Verilog / VHDL x86/x64 Assembler
    $211 (Avg Bid)
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    2 bids
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    LANGUAGE-VHDL Ended

    Use the structural abstraction level of VHDL to write the following program for the DE0 board. Write a VHDL program for a three-digit counter that repeatedly counts from 000 to 199 using seven-segment displays. The counter should have an active-low asynchronous reset input that resets the counter to 000. It should also have an active-low enable input. The counter will change values every 0.25 seconds if the inputs are set appropriately. Your program should use the following three components: 1. A counter that has one output that goes high once every 0.25 seconds. The output should stay high for one cycle of the 50 MHz clock. The counter should have enable, reset, and clock inputs. Use one instance of this component. 2. A four-bit counter that repeatedly coun...

    Verilog / VHDL
    $66 (Avg Bid)
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    programmer for VHDL Ended

    • Train on ball colour. – Ball will be placed about 10cm directly in front of robot. – Measure signals from the camera and estimate the YUV for the ball (for a constant ambient light) • Use hall-effect sensor feedback to control the speed of each wheel • Make robot dribble the ball. i have done half of the code and i need help please

    Circuit Design Electrical Engineering Electronics Engineering
    $204 (Avg Bid)
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    vhdl codes for robotic arm Ended

    i want codes for motors used to drive robotic arm

    Verilog / VHDL
    $207 (Avg Bid)
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    VHDL Design and Simulation of Adders in Xilinx Ended

    VHDL Design and simulation of full adders. Freelancer must have very good knowledge on: full adder 8-bit adder Xilinx software Proficient in English and technical report writting. further step-by step guidance to perform each task will be provided once the freelancer has understood the basic outline of this project. (attached below)

    Electrical Engineering Electronics Report Writing Verilog / VHDL
    $30 (Avg Bid)
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    Single-Cycle Processor Design Ended

    $100/hr Less than 500 lines of source code needed 1-2 hour completion time, if well versed Supporting source code supplied Bonus if completed prior to Saturday I'm working on a pet project, but I'm not incredibly well versed in the language and I must have this finished to complete a gift before Saturday. I have all the necessary sub-modules (some may require minor tweaking), but I need someone with a better understanding of this than me to bang out the top-level modules. I will forward necessary sub-modules and precise specifications upon acceptance of job. For someone with SystemVerilog/VHDL/FPGA experience this shouldn't take more than an hour or two.

    FPGA Verilog / VHDL
    $164 (Avg Bid)
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    Find me a Manufacturer Ended

    ...and I/O ports (DDR3, SATA, HDMI, DVI, USB2, PCIe, UART, I2C) • Experienced with Analog/Digital Design, software/hardware architecture, embedded firmware, board level debug, design, system level integration, hardware design such as implementing hardware circuit blocks in analog and digital, System On Chip, ARM processor, embedded processors, embedded system, microcontroller MCU, FPGA, Verilog, VHDL, ASIC, Digital Signal Processors, MOSFET, FET, IC, electronic components and peripherals, IAR Systems • Building, soldering and modifying circuits, assembly build from Prototype board or main board, transformer, power regulator and power IC, from AC input to DC output. • Experienced in assembly, Serial Peripheral Interface, PCB fabrication, electronic components, PCB ...

    Manufacturing
    $108 (Avg Bid)
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    i need a code using VHDL language Ended

    • Train on ball colour. – Ball will be placed about 10cm directly in front of robot. – Measure signals from the camera and estimate the YUV for the ball (for a constant ambient light) • Use hall-effect sensor feedback to control the speed of each wheel • Make robot dribble the ball.

    C Programming Engineering Software Architecture Software Testing
    $169 (Avg Bid)
    $169 Avg Bid
    2 bids
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    • Make robot dribble the ball using VHDL language Ended

    DIGITAL ELECTRONICS AND VHDL making the robot dribble the ball i am using Quarter and the FPGA devise .

    C Programming Engineering Software Architecture Software Testing
    $23 - $283
    $23 - $283
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    digital clock using vhdl coding. Ended

    digital clock project using VHDL or Block digram in altera software.

    Electronics Verilog / VHDL
    $112 (Avg Bid)
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    1 bids
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    Academic Writing Ended

    1--In the area of Digital Image Processing" An improved Image enhancement in Multiple-Peak Image Based on Histogram Equalization". 2-- Major Project Work on "Designing of 8085 Microprocessor using VHDL".

    Article Rewriting Report Writing Research Writing Technical Writing
    $6 / hr (Avg Bid)
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    VHDL / Verilog coding for Altera Native PHY Ended

    Looking for person with background in VHDL or Verilog and experience with Altera Quartu software and Altera IPs. This job is about debugging/configuring Native PHY for use with SATA protocol. We have most of the design, but some low-level Altera IP configuration is not working correctly. Can provide FPGA board we are using for debugging (within US) if needed. This should be a very quick project for someone familiar with Altera Native PHY and IPs.

    Verilog / VHDL
    $701 (Avg Bid)
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    VHDL / Verilog coding for Altera Native PHY Ended

    Looking for person with background in VHDL or Verilog and experience with Altera Quartu software and Altera IPs. This job is about debugging/configuring Native PHY for use with SATA protocol. We have most of the design, but some low-level Altera IP configuration is not working correctly. Can provide FPGA board we are using for debugging (within US) if needed. This should be a very quick project for someone familiar with Altera Native PHY and IPs.

    Verilog / VHDL
    $1062 (Avg Bid)
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    FPGA Implementation and Analysis of Modified Wallace Multiplier Ended

    Need the detailed analysis after the VHDL code implemented to FPGA.

    FPGA Verilog / VHDL
    $98 (Avg Bid)
    $98 Avg Bid
    8 bids
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    Technology trainers on various technologies Ended

    need trainers on below mentioned technologies: mail me your credentials. Just messag...ARCHITECTURE, SP3D CIVIL, SP3D ELECT, 3DSMAX, ADOBE ILLUSTRATOR, ADOBE INDESIGN, COREL DRAW, ADOBE PHOTOSHOP, ADOBE FLASH, PCB DESIGN, COMPTIA MOBILITY, C/ C++, JAVA CORE & ADVANCE, .NET CORE & ADVANCE, PYTHON, RUBY ON RAILS, PHP CORE & ADVANCE, ANDROID, IOS, SQT MANUAL & AUTOMATION, WEB DESIGNING & DEVELOPMENT, 8051, PIC, ARM, AVR, EMBEDDED C, EMBEDDED LINUX, LINUX DEVICE DRIVERS & DEVELOPMENT, RTOS, VHDL, VERILOG HDL, CMOS & FPGA, SYSTEM VERILOG, PLC, SCADA, HMI NETWORKS & DRIVES, LABVIEW, MATLAB, A+, N+, CCNA, CCNP, LINUX+, SERVER+, CLOUD+, MCSA, MCSE, RHCSA, RHCE, SECURITY+, CEH, CHFI, ECSA, LPT, CYBER SECURITY, MS OFFICE, SAP, ITIL, PMP, SIX SIGMA, SAS, R, SP...

    Analytics CAD/CAM ERP Network Administration Software Development
    $97 (Avg Bid)
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    VHDL coding for Image processing algorithms on xilinx ISE and multisim Ended

    I need vhdl coding for following image processing algorithms on Xilinx ISE and multisim. 1. rgb2gray image conversion 2. ycbcr to rgb image conversion

    Matlab and Mathematica Verilog / VHDL
    $22 (Avg Bid)
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    VHDL data processor Ended

    A data processor which can retrieve the highest byte from a sequence of 500 bytes from a given data generator. The processor must also retrieve the 3 bytes either side of the highest. The index of this highest byte need also be output from the processor, in 12 bit BCD format.

    Verilog / VHDL
    $143 (Avg Bid)
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    c++ and vhdl for fft (parallization and optimization) -- 4 Ended

    design fpga by write c++ code and VHDL code for fast fourier transform algorithm with best optimization and parallelization c++ code for fast fourrier transform algorithim then write it in vhdl and optimize it aftre that convert c++ code by vivado l optimize the code its very important using data flow and nested loop or loop parralization

    C Programming FPGA Verilog / VHDL
    $80 (Avg Bid)
    $80 Avg Bid
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    vhdl for fft (parallization and optimization) -- 3 Ended

    design fpga by write c++ code and VHDL code for fast fourier transform algorithm with best optimization and parallelization c++ code for fast fourrier transform algorithim then write it in vhdl and optimize it aftre that convert c++ code by vivado optimize the code its very important using data flow and nested loop or loop parralization

    C Programming FPGA Verilog / VHDL
    $105 (Avg Bid)
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    Design project Ended

    vhdl for fast fourier transform on fpga

    Branding Corporate Identity Graphic Design Logo Design Website Design
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    NDA
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    Vhdl Code in Xilinx Ended

    I need a vhdl code for xilinx. You can see the project details in file which I have attached

    Electronics Microcontroller Verilog / VHDL
    $37 (Avg Bid)
    NDA
    $37 Avg Bid
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    Academic Writing ( Urgent Project ) Ended

    create a vhdl source file using an editor such as nano and simulate. My budget is less then 70, i will choose a freelancer with best price.

    HTML Java Report Writing Research Writing Verilog / VHDL
    $13 / hr (Avg Bid)
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    Academic Writing ( Looking For A Write Person ) -- 2 Ended

    Its about Computer Systems, i need someone who can do VHDL Assesment for me! Bid if you are the right person! More details in chat!

    Computer Support Report Writing Research Writing Technical Writing
    $5 / hr (Avg Bid)
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    Academic Writing ( Looking For A Write Person ) Ended

    Its about Computer Systems, i need someone who can do VHDL Assesment for me! Bid if you are the right person! More details in chat!

    Report Writing Research Writing Technical Writing
    $5 / hr (Avg Bid)
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    vhdl for fft (parallization and optimization) -- 2 Ended

    design fpga by write c++ code and VHDL code for fast fourier transform algorithm with best optimization and parallelization need to use parallelization technique like (loop parallelism ., function in lining ,, pipeline, data flow ,, resources reusing)

    C Programming FPGA Verilog / VHDL
    $25 (Avg Bid)
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    Computer Systems Ended

    VHDL stands for Very High Speed Integrated Circuit Hardware Description Language and is used to describe electronic hardware. TWO FILES INCLUDED PLEASE READ THEM. Its VHDL Assesment.

    Technical Writing
    $184 (Avg Bid)
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    Write VHDL Code Ended

    I need to track object using particle filter algorithm. Just go through attached PDF. There are various steps. a) One step, Bhattacharya co-efficient calculation, needs square root and divider. I have those calculation. I have attached here too. b) I have attached MATLAB code to generate .coe or .txt files of an image. Either image ca...through attached PDF. There are various steps. a) One step, Bhattacharya co-efficient calculation, needs square root and divider. I have those calculation. I have attached here too. b) I have attached MATLAB code to generate .coe or .txt files of an image. Either image can be provided from testbench using text file or .coe file can be stored in BRAM. I need, 1. VHDL Code (Comments are compulsory) 2. VHDL Testbench 3....

    FPGA Imaging Verilog / VHDL
    $102 (Avg Bid)
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    digital system design Ended

    stepper motor sequencer using vhdl code

    Verilog / VHDL
    $51 / hr (Avg Bid)
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    digital electronic design FPGA based Ended

    Electronics Engineer - FPGA based designs We are looking for an experienced electronics design engineer who will...FPGA's for applications in industrial ink jet printing. You will work with an experienced team of mechanical, fluids dynamics, physicists, software and engineers designing industrial ink jet printer systems using multiple ink jet technology platforms. You will be involved and/or be responsible for designing electronics circuits and boards incorporating FPGA's, coding, implementing and testing VHDL or verilog firmware associated with these future boards. You will also be involved or responsible for maintaining and adding features to an existing FPGA source code written in Verilog. Some projects involve the design of electronic circuitry to interface to A/D a...

    Engineering
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    VHDL help required required Ended

    I have a small project coming in next few days and need help in VHDL. All other details will be posted in upcoming days.

    C Programming Embedded Software Engineering Software Architecture Verilog / VHDL
    $89 (Avg Bid)
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    Cryptography And VHDL Ended

    Hello, I have a cryptography (Blowfish ) code in PHP I want you to convert it into the code in VHDL. I want you to describe its simulation as complete as possible.

    Cryptography Verilog / VHDL
    $186 (Avg Bid)
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    Error Emulation model Ended

    design a structural 16-bit floating point adder and integrate it with error-injection model(VHDL)

    Verilog / VHDL
    $250 (Avg Bid)
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    1 bids
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    vhdl for fft (parallization and optimization) Ended

    design fpga by write c++ code and VHDL code for fast fourier transform algorithm with best optimization and parallelization

    C Programming FPGA Verilog / VHDL
    $105 (Avg Bid)
    $105 Avg Bid
    2 bids
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    Project for ahmedmohamed85 Ended

    Hi Ahmed, we have an immediate need for debugging codes written in VHDL for FPGA device. Please contact us.

    Electrical Engineering Electronics Engineering Microcontroller Verilog / VHDL
    $150 (Avg Bid)
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    Write some Software Ended

    Need someone who is familiar with VHDL software written for FPGA devices. There is a bug in the software that was written that has to be debugged.

    PHP Software Architecture
    $238 (Avg Bid)
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    QuestaSim Debug Some Code Ended

    The task is to debug and simulate some simple code in VHDL by using QuestaSim.

    FPGA Verilog / VHDL
    $94 (Avg Bid)
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    Real Time Software Engineer Ended

    Systems and Software projects Technical Responsible Real Time embedded SW development and validation for space microprocessors: Low level SW integration within microprocessors / FPGA solutions Hardware dependent software, communication drivers and protocols Real time multithread applications Integration of VHDL modules for Real Time requirements (VHDL & SW) SW Systems modeling and validationRequirements: Education:Bachelor’s Degree in Computer Engineering, Computer Science, Telecommunication Engineer or other similar Technical discipline. Advanced degree or an equivalent combination of education and experience a plus. Required Experience/Skills: Three (3) or more years of experience in Real Time software development in C/C++. Strong knowledge of embedded real time s...

    App Developer HTML Mobile App Development PHP Sharepoint
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    Design a 8x8 DCT and IDCT for JPEG Ended

    i need a 8x8 DCT and IDCT designed in VHDL

    Verilog / VHDL
    $61 (Avg Bid)
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    FPGA Framework Xilinx Ended

    ...shall be designed for a Kintex UltraScale Devboard; The main functionality of this system is a pattern generator and an acquisition system. The System shall be controlled from Matlab through an API running simple commands/functions communicating with the FPGA through UART and Ethernet (full support in both). The outcome of the project shall be an environment that is easy to maintain and develop further. The FPGA shall implement an infrastructure consisting of JTAG, Timers, DDR, UART, Ethernet, BRAM, Registers, Microblaze etc. The AXI Ethernet and DMA from Xilinx shall be used in the design, see i.e. page 70 in: Host Computer

    Electronics Embedded Software FPGA Matlab and Mathematica Verilog / VHDL
    $705 (Avg Bid)
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    16-bit floating point adder Ended

    Design a 16-bit floating adder in VHDL. Modelsim for simulation and quartus for synthesis

    Verilog / VHDL
    $155 (Avg Bid)
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