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    4,795 verilog vhdl jobs found, pricing in USD

    I need to do Soundex Algorithm in VHDL language in Xilinx software. A simple name as the input for example my name 'NAUFAL' => then will be converted based on the soundex algorithm and table => and will give the output of 'N160'. I already make the research and I will provide all the details needed such as the description of soundex, flowchart, and etc. Hope to hear from you asap. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Del...

    $85 (Avg Bid)
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    1 bids

    I have three questions related with VHDL. YOu have to write the complete State machine and then VHDL code for each problem in the tool called "XILINX". The questions are not difficult. Please read the attached file for the description of each question. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all others including desktop s...

    $80 (Avg Bid)
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    5 bids
    VHDL Ended

    2 questions to solve using VHDL, code must work properly though implementation is not important. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all others including desktop software or software the buyer intends to distribute: A software installation package that will install the software in ready-to-run condition on the platform(s) specified i...

    $72 (Avg Bid)
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    2 bids

    MPEG-2 video encoder project. I have the block diagram as well as the specifications. Need Verilog HDL coding for the encoder. Major blocks include Discrete cosine transform, Quantization, Run length encoding and Motion estimation. The input to the encoder is taken in YUV format from a camera source. A completed project would be paid $300. Deadline for this project is dec 25th, 2007. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be insta...

    $255 (Avg Bid)
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    Please see attached document for details VHDL Code and Testbed for System Required (Simulation Optional) Simple Arithmetic operations Needed ASAP (within 24Hours) Thanks in advance! ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all others including desktop software or software the buyer intends to distribute: A software inst...

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    I'm in need of a detailed guide to VHDL syntax. You can use this as a guide but don't put in any examples, just syntax. I don't want you to copy this link exactly either, put it into your own words. Here's the link, and add what's missing to this link: <> ## Deliverables Rent A Coder requirements notice: As originally posted, this bid request does not have complete details. Should a dispute arise and this project go into arbitration "as is", the contract's vagueness might cause it to be interpreted against you, even though you were acting in good-faith. So for your protection, if you are interested in this project, please work-out and document the requirements onsite. 1) Complete and fully-functional working

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    hey I wanted the vhdl code for the following..... could you help me out with this..... --Design and synthesize a simple vending machine on the Spartan 3 or Spartan 3E board with the following features: --􀂾 The vending machine has four products. They cost 75, 80, 85, or 90, cents each. Use the slider switches (SW0 thro SW3) to select one of the products. --􀂾 Use two of the seven segment displays (or the LCD) to display the cost of the product entered --􀂾 Assume the vending machine only accepts $1 bills. Press BTN0 to pay for the product. --􀂾 Dispense the product by activating an appropriate solenoid (turn on an LED for 1 second to indicate the specific product is being dispensed) --􀂾 Using the other two seven segment displays show the change required

    $25 - $30
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    Hi all, We are looking for a Software engineer which will cooperate with my company's engineers and developers, in the development of a new product. In general, the product is an electronic device which acts as a voltmeter. The selected engineer will have to write the software part for the used hardware. The technical knowledge required is as follow: VHDL Language, Xilinx or Altera tools, Modelsim for simulation, Writing Test benches. The most important issues are the candidate's communication skills and loyalty. The company team includes employees from all over the world (India, USA, Israel, Macedonia..), and therefore professionalism, commitment and dedication are required. This is a very serious and multi modules project with tight deadlines. Workers of...

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    28 bids

    Delhi public school problem ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's enviro...on the platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement...

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    Hi all I'm having a trouble in chip design work. I want an program source code (in any programming language) that - Import any designs based on VHDL source code or netlist exported from Xilinx or Altera Development Tool (Quartus, ISE,...) - Parse and Implement any algorithm that will modify the design to give an new design which power consumpt is reduced - Certainly, output is the new power optimized netlist or VHDL source code that can be imported again to Quartus or ISE (xilinx). To prove that power consumption has been reduced in modified design, I will test base on power estimate tool of Quartus or ISE. Although these development tools have optimized power when synthesis but I want to do it myself. So you can use any algorthm that can optimize power such as RTL isola...

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    I have a design that needs verilog code written to act as a JTAG TAP Master. It gets commands and data from another chip and needs to output JTAG commands. This all needs to fit into a 64 macrocell CPLD. This project will be worked on together as I will provide logic traces and you will program the verilog so the jtag signal closely matches the logic traces. I wish for someone to be in Northamerica so the time-zones are close enough for real-time communications. Please send me a PM if you are interested and I will post the logic traces for you to examine. This project is VERY SIMPLE (how complex can you get with 64 macrocells =D)

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    A VHDL school project is required. The task is to designe and implement a microprocessor with 10 - 15 instructions and with the ability to add 3-4 more easily in the future. The instructions will be defined with / by the coder who will win the bid. These instructions are ADD, SUB, OR, AND, XOR, some instructions to compare data and jumps are required. You will need to define an architecture of microprocessor to accomplish these instructions (1, 2 or 3 buses) and to implement it in VHDL. For the design phase some drawings will be required to express the solution (e.g.: buses, registers, ...). For the implementation part comments are required so that I can easily understand how it works. Also, some support from your side after the project is finished will be highly apreciated i...

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    Implement a special efficient pipelined DDR-SDRAM controller into a Spartan 3 FPGA as described in the attached docuement ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all others including desktop software or software the buyer intends to distribute: A software installation package that will install the software in ready-to-run condition on the platf...

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    Urgent VHDL project till 10.06.2007!!! ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all others including desktop software or software the buyer intends to distribute: A software installation package that will install the software in ready-to-run condition on the platform(s) specified in this bid request. 3) All deliverables will be considere...

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    Implement a special efficient pipelined DDR-SDRAM controller into a Spartan 3 FPGA - Pipeline (incl. bank switching) - Read a 64bit value - incremet and write back the 64 bit value to the same adress - during wait cycles on the one bank the...bank the same process should run on the other bank (alternating) - total 4 independant DDR-SDRAMs connected to the Spartan3 - SDRAM type: V58C2512164SAJ-5 - Spartan3: XC3S1500FG676 - speed: DDR SDRAM clock min 96 MHz, no "NOP" cycles in access - hardware already available We provide UCF-file and Verilog interfaces to our logic. If necessary we can provide an evaluation hardware. Expected deliverals: Xilinx ISE 9.1 project including well-documented Verilog sources and simulation We will check for pro...

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    We are in need of a simple C# GUI tool to generate and parse Verilog module hierarchies. The software must have the following capabilities: - Represent a Verilog design in an editable graphic format, like the schematic style of a regular electric/digital/UML schematic application. In the main window, it should be possible to add new modules (graph nodes), new signals (graph edges) and modify them as in any Windows GUI application (eg drag and drop, undo and redo, etc.). A secondary window should display the hierarchy in a graphical tree. The GUI must be designed in a C# tool like Microsoft Visual .NET (Express edition is ok). A design should be loaded and saved in an XML file. - Parse a group of Verilog code design files and extract the hierarchy of modules they contai...

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    attached are the complete requirements ... ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the...on the platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ...

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    VHDL Ended

    attached are the complete requirements ... ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the...on the platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ...

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    HDL Ended

    Using Aldec’s Active-HDL Version 6.3 Student Edition design tool, develop a Verilog description and a schematic of the MINIMIZED COMBINATIONAL DIGITAL LOGIC FUNCTION BELOW: - Use K-MAP method to minimize the following boolean expression in S-o-P Form. F(A,B,C,D)= (ABC + !A!B) (C + D) ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all other...

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    Hi, I have 2 problems of asynchronous sequential circuit problems to be solved. I need these done as soon as possible. Attached are the problems in a doc file, thank you for bidding. please bid for all the problems, if you cant, bid according to how many prpblems u can solve. ## Deliverables 1) Complete and fully-functional working program(s) in...on the platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ## Platform VHDL,...

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    Hi, please see the attached file. I need this lab to be done in VHDL code, also, i use xilinx 8.0 and 9.0 and you can download a free at xilinx web pack. need this done withn 1 day or so. but try to get as much as you can . thank you ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all others including desktop software or soft...

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    Hi, I have 2 problems of asynchronous sequential circuit problems to be solved. I need these done as soon as possible. Attached are the problems in a doc file, thank you for bidding. please bid for all the problems, if you cant, bid according to how many prpblems u can solve. ## Deliverables 1) Complete and fully-functional working program(s) in...on the platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ## Platform VHDL,...

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    See the attachement. In the attachment, Lab and MY4ALU are already done. Now, read the Lab 2. doc, i use xilinx 9.1i, and i need this done within 1-2 days without no errors. Previous coder did not do well, I have 3 more similar project and the winning coder will get more work. let me know if you have any questions. thank you ## Deliverables 1) Co...on the platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ## Platform ...

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    See the attachement. In the attachment, Lab and MY4ALU are already done. Now, read the Lab 2. doc, and i need this done within 10 - 15hrs or soon. thank you ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on...on the platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ## P...

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    hi, i need help on a lab, attached is what to do, you should have experience with Xlinx ISE tool, its a 4 bit ALU design. should provide the output and benchwave form results. Need this within 10- 12 hrs from now. thank you more work will be given throughout this year. so more work from me to the coder. ## Deliverables 1) Complete and fully-functional working progr...on the platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ## Pla...

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    hi, i need help on a lab, attached is what to do, you should have experience with Xlinx ISE tool, its a 4 bit ALU design. should provide the output and benchwave form results. Need this within 10- 12 hrs from now. thank you more work will be given throughout this year. so more work from me to the coder. ## Deliverables 1) Complete and fully-functional working progr...on the platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ## Pla...

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    hi, i need help on a lab, attached is what to do, you should have experience with Xlinx ISE tool, its a 4 bit ALU design. should provide the output and benchwave form results. Need this within 10- 12 hrs from now. thank you more work will be given throughout this year. so more work from me to the coder. ## Deliverables 1) Complete and fully-functional working progr...on the platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ## Pla...

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    A VHDL school project is required. The task is to designe and implement a microprocessor with 10 - 15 instructions and with the ability to add 3-4 more easily in the future. The instructions will be defined with / by the coder who will win the bid. These instructions are ADD, SUB, OR, AND, XOR, some instructions to compare data and jumps are required. You will need to define an architecture of microprocessor to accomplish these instructions (1, 2 or 3 buses) and to implement it in VHDL. For the design phase some drawings will be required to express the solution (e.g.: buses, registers, ...). For the implementation part comments are required so that I can easily understand how it works. Also, some support from your side after the project is finished will be highly apreciated i...

    $113 (Avg Bid)
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    I need a expert in VHDL/Verilog behavioral. If you are please PM me, for more info on the project. Thank you

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    I need somebody to quickly translate 550 lines (includes comments) of Verilog code to VHDL. The code is for a state machine and has no complicated constructs. Comments must be conserved and signal names will need to be prefixed with s_, variable names with v_, input ports with i_, output ports with p_, etc. The resulting VHDL code must compile. We will not be doing a functional test and will only be inspecting your work visually for translation accuracy and style. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side ...

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    I will keep this simple. I require a circuit diagram and VHDL code for an 8 bit LFSR (Linear Feedback Shift Register) I also require a circuit diagram and VHDL code for an MISR (Multiple Input Shift Register). If you have experience with VHDL you will realise that I intend to put together a Built-in-Self-Test circuit simulation. The LFSR and MISR VHDL code should be able to work with a CUT (Circuit Under Test) that has 8 inputs and 8 outputs. The CUT will also have to be coded in VHDL. In addition I would also require the support files for the VHDL code. Any bidder with VHDL experience will understand exactly what I mean and what I have described above. This is a relatively small project and shouldn't take very long, if you have the rel...

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    Its basic VHDL assignment to deisgn muxes,... It has to be compiled on the VHD Compiler under Cadence OrCAD (Affirma Design and Verification ) . I need the code(VHDL) file, testebenches and the README file for all of the 6 questions. Its due hours from now. If you are interested , contact me ASAP. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer&#...

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    The project would be to create a game based on the Xilinx Virtex II Pro board. The game shall be a simple one such as Tic-tac-toe, or Pong, or etc. The game would be programmed for the Virtex II Pro board and the graphics displayed on a VGA monitor. Inputs to control the game will be from the Virtex II Pro board The bidder for the project should be good in either Verilog or VHDL in order to code the game for the Virtex II Pro board. The manual for the board used for this project: Xilinx Virtex II Pro Manual Please bid if you are confident of creating a simple game within a short time span of around 2weeks. We shall then discuss more about the requirements and budget. Thank you.

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    ...for choice. circuit design methodology, including considerations of BIST/JTAG if included. of test bench waveforms, with explanation of strategy used. results, analysis and discussion. on results of practical demonstration using development board. g.Conclusions. h.References. , containing printouts of the circuit schematic or VHDL coding, test bench waveforms, placement & routing and results of all simulation work. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended

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    ...visit our office to understand the requirements. Engineering graduate / post graduate from premier Institutes > 4 years of experience in a leading IC/Software company Should be willing to work on part time / full time basis Should be willing to work on project basis Expertise in C++, SystemC System level modeling SystemC based behavioral models Exposure to VHDL, Verilog will be a plus Understanding of SoC/ ASIC Design flow Working with global clients ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server...

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    Hi to all . The purpose of this simple verilog HDL work is to select the best coder for a much bigger project whose price range would be between 1000-1200 USD $. But to make sure I select the right person this is a simple work that I want you to do first. **The attached file contains all the description of the work that you need to do. This is a very simple work for the person who is a real expert in Verilog HDL.** Feel free to ask any questions . ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intende...

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    Verilog PID Implmentation for use on a Xilinx Spartan 3E chip. The program would have user selectable PID parameters as well as a selectable setpoints. ## Deliverables Rent A Coder requirements notice: As originally posted, this bid request does not have complete details. Should a dispute arise and this project go into arbitration "as is", the contract's vagueness might cause it to be interpreted against you, even though you were acting in good-faith. So for your protection, if you are interested in this project, please work-out and document the requirements onsite. 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending...

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    ...in SystemC and scan it and parse it using any freeware tools (like flex, bison, Antlr ...) and then translate the output object model from this tool to and intermediate format called "Control Data flow Graph CDFG". The format of the CDFG is explained in the attached paper. I need Source code written in C++ and can be compiled by VC++ Ver6 or later. The attached paper explain a translator from VHDL to CDFG I just want like it but from SystemC to CDFG. So,the general idea is: 1. create the BNF, test out on C++ and SystemC tests 2. create an object model for the synthesizable constructs 3. create a cdfg on select constructs Code should compile on VC6 ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as comple...

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    I require a (Altera)NIOS II, CPU processor to be enhanced, i require the interrupt controller to support 32 UARTS and Interrupts from Timers,EPCS and the LAN. Ideally i require the system to have 36-38 Interrupts. Requirements. VHDL source for new Interrupt Controller Details of how to integrate into NIOS II and Quartus Example C Source for Setup of new controller. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installe...

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    Controller for the PS/2 interface of the XSA-50 board. • Design in VHDL • Bidirectional communication with the keyboard • Communication with the mouse • Implementation on the XSA-50 board PS/2 port ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows? (depending on the nature? of the deliverables): a)? For web sites or? other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all others including desktop software or software the buyer intends to distrib...

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    We require a good VHDL programmer to modify some existing VHDL source code which currently interfaces with a CMOS imaging sensor and modify the source code to interface a video decoder ic (ADV7183). The source code at the moment interfaces one CMOS sensor, we require it to interface 4 video decoder ics (only one at once). ## Deliverables Working modified VHDL source to interface 4x ADV7183 video decoders, compress the captured image (video compression routines are already written and will be sent upon bid acceptance) and output to our microprocessor. The use of our CVS server during development is encouraged so that we can take an active involvement in the development process if required. ## Platform VHDL - Spartan III

    $7547 (Avg Bid)
    $7547 Avg Bid
    3 bids

    I need a proficient VHDL coder to help me build some specific components of a few architecture implementations; especially basic radix-8 algorithms? including multiplexer, adder and subtructer.. Further details can be discussed. (Implementations will be easy and wont take too much time.) ## Deliverables Rent A Coder requirements notice: As originally posted, this bid request does not have complete details. Should a dispute arise and this project go into arbitration "as is", the contract's vagueness might cause it to be interpreted against you, even though you were acting in good-faith. So for your protection, if you are interested in this project, please work-out and document the requirements onsite. -- ## Platform Windows XP or Linux

    $318 (Avg Bid)
    $318 Avg Bid
    2 bids

    I'm looking to build a relationship with a few coders for various bits of work - web (LAMP based - Perl/PHP, AJAX etc - all the corportate buzzwords) as well as web GUI design, video processing (C++ or similar), firmware (PIC family assembler), FPGA development (VHDL and Altera QuartusII visual code) and so on. This is a trial project to see how you work in the area of video processing in a windows/linux PC environment. It is quite simple, but I have been told that I need to sort out the quality of coders on here. This particular project: Unit 1: - Take a number of MPEG video files, and break them down frame by frame into audio and video (e.g single picture frames and 1/25 sec audio slices). - Digest each frame+audio into a number of separate 1-byte fingerprints (e.g. average H...

    $30 - $100
    $30 - $100
    0 bids

    i need a vhdl code for a test pattern generator(tpg). the codes should work when synthesised and simulated using xilinx. The design for tpg is taken from paper.i've attached the paper. i can synthesuse ans simulate myself i need the codes for lfsr as well which is used in the tpg. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all...

    $46 (Avg Bid)
    $46 Avg Bid
    3 bids

    Hi there guys. I have an essay on VHDL language , and as most people I am crap when it comes to programming. The essay contains some exercises that have to be completed in order to built an alarm clock, I think its straight forward for somenone who knows how to program. In more details I have attached the full discrition of this is important that I get this essay in 3 weeks time. Thank you guys ,and happy bidding ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's ...

    $56 (Avg Bid)
    $56 Avg Bid
    5 bids
    vhdl Ended

    vhdl..with activehdl ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all others including desktop software or software the buyer intends to distribute: A software installation package that will install the software in ready-to-run condition on the platform(s) specified in this bid request. 3) All deliverables will be considered "work made ...

    $25 - $30
    $25 - $30
    0 bids

    I need someone to write me vhdl code for the project enclosed. It was done in matlab but I need it synthesized in vhdl. I need this done in 7 days. I need the waveform explained in detail. You can use Modelsim or Xilinx if you wish. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all others including desktop software or software the buyer ...

    $30 - $5000
    $30 - $5000
    0 bids

    Circuit design for Lattice CPLD/MachXO. VHDL or Verilog. Interface to the Netburner processor module (see MOD5282). Timers. Encoders input processing. Counters. Pulse Width measurement. Ouput Compare Triggers. 32Bit Multiply and Shift operations. State Machine. We will submit more details upon acceptance. Duration 30 Days max. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the...

    $206 (Avg Bid)
    $206 Avg Bid
    4 bids